1. Field of the Invention
This invention relates to semiconductor devices and, more particularly, to semiconductor devices based on Group IV elements.
2. Art Background
The desirability of fabricating devices based on Group IV elements, such as silicon, by building the device within an electrically insulated semiconductor region has long been realized. Such an insulated device has many advantages over a conventional device that is formed directly on a silicon substrate. In a conventional device radiation such as alpha particles produces carriers in a conducting substrate and these carriers introduce spurious signals in the active region of the semiconductor device. In contrast, for an insulated device such radiation produces carriers in a silicon substrate but these carriers cannot migrate through the insulating layer. Thus, spurious signals in the active region are not produced. Further devices built on insulators offer the possibility of lower capacitance and thus faster switching times than conventional devices. Finally, since the active semiconductor regions of insulated devices are electrically isolated, these separate regions are maintainable at different potentials without undesirable interactions.
To obtain the advantages of insulated devices utilizing Group IV semiconductor materials, numerous technologies have been developed. However, all of these approaches involve elaborate procedures that do not easily lend themselves to other than laboratory production techniques. For example, a large experimental effort has been devoted to forming silicon devices on sapphire substrates. The production of a high quality silicon epitaxial layer on a sapphire substrate is extremely difficult and costly. Thus, devices to meet exacting specification are not produced by the silicon on sapphire technique.
Similarly, techniques have been developed for producing single crystals of silicon on insulators such as silicon oxides. Representative of these techniques are the dielectric isolation processes. (These processes are described by K. E. Bean and W. R. Runyon, Journal of the Electrochemical Society, 124, No. 1, p. 5C, (1977).) Dielectric isolation entails a multistep, elabrate procedure that is shown in FIG. 1. Initially, a substrate of high quality silicon is prepared. This silicon substrate, 1 in FIG. 1, is coated with an insulating material such as silicon oxide, 3, and holes, 5, are formed in the oxide by conventional techniques, e.g., photolithography followed by anisotropic chemical etching. Grooves, 7, are then etched in the exposed portions of the silicon underlying the holes in the dielectric material. These grooves, 7, are epitaxially coated with a layer of N.sup.+ silicon, 8. The N.sup.+ silicon is, in turn, coated with an insulator, 9, such as silicon oxide. The insulator is once again, in turn, coated with a layer of polysilicon, 10. The structure produced is shown in FIG. 1F. The entire structure is then inverted and the silicon substrate 1, is ground off until the structure shown at 1G is obtained. In this structure, the remaining high quality silicon is denoted by 12, insulating layers are indicated by 14 and 15, and polysilicon is indicated by 16. Thus, the final structure has single crystal silicon, 12, on an electrically insulating material. In this manner, the active region of the silicon device is electrically insulated with the resulting reduction of spurious signals and switching time.
As can be appreciated from the description and from FIG. 1, dielectric isolation involves a multitude of complicated processing steps. Thus, this technique has only been used for applications which require production of devices where properties are critical and where expense is a secondary factor. Although the production of devices within an electrically insulated Group IV semiconductor region has been shown to have great advantages, the production of such devices by a process that is easily adaptable to other than laboratory procedures has been difficult.